1. Field of the Invention
Embodiments of the present invention relate to semiconductor testing.
2. Description of the Related Art
Testing is an important step in the production of semiconductor devices for use. Typically, partially or fully completed semiconductor devices may be tested by bringing terminals disposed on an upper surface of a device to be tested—also referred to as a device under test (or DUT)—into contact with resilient contact elements, for example, as contained in a probe card assembly, as part of a test system. A test system controller may be coupled to the probe card assembly to send and receive test signals to and from the DUTs over a set of test channels. A test system controller with increased test channels can be a significant cost factor for a test system. Test system controllers have evolved to increase the number of channels and hence the number of devices that can be tested in parallel (sometimes referred to as multi-site testing).
During testing, some test channels provide test input signals to input pins of the DUTs, others test channels monitor for test result signals from output pins of the DUTs, and still others provide test input signals to, and monitor for test result signals from, input/output (IO) pins of the DUTs. Tester logic can be coupled to the test channels for generating the test input signals and/or processing the test result signals. The tester logic can be part of the test system controller. Some tester logic can include more test circuits than are required for any one test application. Test circuits that are not used in a given test application are nevertheless present and can interfere with the intended operation of test equipment. Other tester logic, while programmable, can make implementation of certain types of test circuits inefficient, impracticable, or even impossible.
Accordingly, there exists a need in the art for a method and apparatus for testing semiconductor devices that attempts to overcome at least some of the aforementioned deficiencies.